MOST

Electric Vehicle(EV) has been a priority topic...

read more >>

BMBF

 Electromobility is one of the key technologies...

read more >>

 

Innovative Electronic Control Units


In this project, we build the Electronic Control Unit from off-the-shelf components to reduce costs. The off-the-shelf components are minimally modified to make the complete system deterministic, reliable and automotive certifiable. Some of the early outcome of the research is published in reputed conferences/workshops such as HiRES 2013, DATE 2013, ASAP 2013 and DSD 2013. A lab course, “Hardware/Software Co-Design with a LEGO car” at TUM is being conducted to disseminate latest research among students.

 

 

Modern high-end cars contain ~100 distributed Electronic Control Units (ECUs) and ~4 Km long cables to carry out complex functionalities with distinct requirements. Typically, these functionalities can be classified in any-time (infotainment), soft real-time (displays) and hard real-time (break). The functionalities embedded in the cars are expected to grow resulting in more number of integrated ECUs and cables. Such distributed Information and Communication Technology (ICT) infrastructure results in ever increasing weight, cost and complexity of modern automobiles. The project aims to build a centralized ICT infrastructure for future Electric Cars (eCars) to drastically reduce number of ECUs and cables.

The research interest within this context centers around novel concepts for hardware, software, and hardware/software co-design for future inner/inter-car ICT infrastructure, including but not limited to MPSOC-based ECUs, distributed control and battery management systems, formal verification, and model-based programming paradigm. Even though the scientific activities include a high degree of fundamental research, it involves regular contacts with renowned German automobile manufacturers as well as their partners in China.

 

OpenCL Lane Detection on heterogeneous platforms ( in lab | at night | in the day ). The algorithm can achieve peak performance 640 and 486 frame per second on NVIDIA GTX 660 TI and STRATIX V FPGA, respectively. The same algorithm can also run 45 frame per second on the CYCLONE V FPGA.